Forwarding element integrated circuit chip with separate i/o and switching tiles

ABSTRACT

Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections. In some embodiments, the main die and the IO dies make all connections through microbumps on the silicon interposer and some microbumps connect to external components using through-silicon vias (TSVs). The microbumps of the main die, in some embodiments, are arranged so that they are mirrored on either side of the main die and rotationally invariant under a 180 degree rotation. IO dies, in some embodiments, are mounted in a first orientation to connect to a first side of the main die and a second rotated (by 180 degrees) orientation to connect to a second opposite side of the main die.

CLAIM OF BENEFIT TO PRIOR APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/896,018, filed Feb. 3, 2018. U.S. patent application Ser. No.15/896,018 claims the benefit of U.S. Provisional Patent Application62/612,059, filed Dec. 29, 2017. The entire specifications of all ofthose patent applications are hereby incorporated herein by reference intheir entirety.

BACKGROUND

The ever-increasing demand of higher bandwidth switching chips forcesearlier adoption of the latest technology nodes (e.g., ≤7 nm).Monolithic die solutions require that a serializer/deserializer(SerDes), a key element of all switching ASICs, must be available on thesame technology nodes as the core logic. A solution that breaks thedependency on SerDes availability on a same technology node as ahigh-bandwidth switching chip ASIC needs to be developed.

SUMMARY

Some embodiments of the invention provide a novel method and chip designfor a forwarding chip, that decouples input-output (IO) technologyrequirements from the technology used in a high bandwidth switchingASIC. In some embodiments, a main die including a latest generationswitching chip is coupled to a set of 10 dies (e.g., SerDes dies). Themain die, in some embodiments, uses a latest technology (e.g., 7 nmnodes) while the IO dies, in some embodiments, use a more maturetechnology (e.g., 16 nm nodes).

Some embodiments provide multiple IO dies that each provide connectivityto external components to the high bandwidth switching ASIC (e.g., acore ASIC die). The multiple dies are mounted on a silicon interposer,in some embodiments, using microbumps to make the connections betweenthe dies and the silicon interposer. Additional connections to the padare made from each die including to general purpose input-output (GPIO)connections. In some embodiments, the main die and the IO dies make allconnections through microbumps on the silicon interposer and somemicrobumps connect to external components using through-silicon vias(TSVs). The microbumps of the main die, in some embodiments, arearranged so that they are mirrored on either side of the main die androtationally invariant under a 180 degree rotation. IO dies, in someembodiments, are mounted in a first orientation to connect to a firstside of the main die and a second rotated (by 180 degrees) orientationto connect to a second opposite side of the main die.

A novel protocol for performing register read and write access fordifferent groups of SerDes (e.g., a group of 8 56 Gbps SerDes) within aSerDes die is provided for some embodiments. In some embodiments, thenovel protocol uses a set of 5 pins including a management clock input(MCI) sent from the main (core) die (tile) to the IO die (tile), amanagement data input (MDI) of the IO die used to command, address, andwrite data, a management clock output (MCO) of the IO die that sends theMCI clock back from the IO die to the main die in order to capture themanagement data output (MDO) from the main die, and a management dataoutput (MDO) of the IO die used to read data back to the main die. Theprotocol includes transactions for read transactions, writetransactions, reset transactions, control and status register (CSR)access, and an interrupt transaction. The protocol in some embodimentsalso includes burst read and write operations, atomic operations, etc.

The preceding Summary is intended to serve as a brief introduction tosome embodiments of the invention. It is not meant to be an introductionor overview of all-inventive subject matter disclosed in this document.The Detailed Description that follows and the Drawings that are referredto in the Detailed Description will further describe the embodimentsdescribed in the Summary as well as other embodiments. Accordingly, tounderstand all the embodiments described by this document, a full reviewof the Summary, Detailed Description and the Drawings is needed.Moreover, the claimed subject matters are not to be limited by theillustrative details in the Summary, Detailed Description and theDrawings, but rather are to be defined by the appended claims, becausethe claimed subject matters can be embodied in other specific formswithout departing from the spirit of the subject matters.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a simplified view of a forwarding chip according tosome embodiments.

FIG. 2 conceptually illustrates functionality of aserializer/deserializer (SerDes) die.

FIG. 3 illustrates a set of connections used by a single lane of aSerDes die.

FIG. 4 illustrates a set of connections for a set of 8 lanes in a SerDestile that includes a set of management interface connections.

FIG. 5 illustrates one embodiment of a forwarding chip.

FIG. 6 conceptually illustrates a process for assembling a forwardingchip.

FIG. 7 illustrates different arrangements of SerDes tiles in embodimentsof the forwarding chip that make use of different connections betweenthe SerDes tiles and the main die.

FIG. 8 illustrates a receive interface timing diagram using a sourcecentered receive clock forwarding scheme.

FIG. 9 illustrates a maximum setup and maximum hold timing budget.

FIG. 10 illustrates a transmit interface timing diagram using a sourcecentered transmit clock forwarding scheme.

FIG. 11 illustrates a transmit clock setup that defines the setup timebetween the worst transmit data bit and a transmit clock rising edge,and defines a transmit clock hold that defines the hold time between theworst transmit data bit and the transmit clock rising edge.

FIG. 12 illustrates a complete datapath for a transmit interface of someembodiments.

FIG. 13 illustrates a datapath for management interface clocking.

FIGS. 14A-B illustrate a timing diagram of a successful and failed readoperation.

FIGS. 15A-B illustrate a timing diagram of a successful and failed writeoperation.

FIG. 16 illustrates a timing diagram for a reset operation.

DETAILED DESCRIPTION

Some embodiments of the invention provide a novel method and chip designfor a forwarding chip, that decouples input-output (IO) technologyrequirements from the technology used in a high bandwidth switchingASIC. In some embodiments, a main die including a latest generationswitching chip is coupled to a set of IO dies (e.g., SerDes dies). Themain die, in some embodiments, uses a latest technology (e.g., 7 nmnodes) while the IO dies, in some embodiments, use a more maturetechnology (e.g., 16 nm nodes).

Some embodiments provide multiple IO dies that each provide connectivityfor external components to the high bandwidth switching ASIC (e.g., acore ASIC die). The multiple dies, in some embodiments, are mounted on asilicon interposer using microbumps to make the connections between thedies and the silicon interposer. Additional connections to the pad aremade from each die including to general purpose input-output (GPIO)connections. In some embodiments, the main die and the IO dies make allconnections through microbumps on the silicon interposer and makeadditional connections through microbumps connected to through-siliconvias (TSVs) to connect to external components.

FIG. 1 depicts a simplified view of the forwarding chip 100 includingsubstrate 120, main die 105, SerDes tiles (dies) 110, and connections115 between the main die 105 and the SerDes tiles 110. In someembodiments, substrate 120 is a silicon interposer that includes a setof microbumps on one face to which main die 105 and SerDes tiles 110form connections. The set of microbumps includes microbumps that formconnections between main die 105 and SerDes tiles 110, as well asmicrobumps that connect to through-silicon vias (TSVs) that provideconnections with external components. In some embodiments, the externalconnections are made through a pad that provides the connectivity toexternal components.

The separation between the main die containing switching logic or fabricand a set of IO dies (e.g., SerDes dies or tiles) allows for integratingdifferent technology standards (e.g., a 7 nm based main die integratedwith a 16 nm based SerDes tile). The separation also allows each element(i.e., switching fabric and IO die) to be improved separately withouthaving to redesign an entire die when only one component of the chipfunctionality is being improved. Incremental improvements are thus ableto be made more easily and alternative chip designs can be developedthat take advantage of a pre-existing IO or main (e.g., switchingfabric) die.

Each SerDes die comprises multiple SerDes functional units. FIG. 2illustrates a block diagram of a SerDes die using 68, 56 Gbps (56G)SerDes along with additional functions necessary for a SerDes die tosupport. FIG. 2 includes a set of 56G SerDes 205, a set of connectionsto GPIO interfaces 210, auto-negotiation and link training modules 215,microbumps 220, management interfaces 225 for sets of 56 Gbps SerDes,and a global management interface 230. Each 56 Gbps SerDes provides aSerDes service for 32 bits of data in both the transmit and receivedirection sent with a frequency of approximately 1.75 GHz for a total of56 Gbps. In other embodiments, pairs of 56 Gbps SerDes are replaced by a112 Gbps SerDes that provides a SerDes service for 64 bits of data inboth the transmit and receive direction sent with a frequency ofapproximately 1.75 GHz for a total of 112 Gbps. In other embodiments,pairs of 56 Gbps SerDes are replaced by a 112 Gbps SerDes that providesa SerDes service for 32 bits of data in both the transmit and receivedirection sent with a frequency of approximately 3.5 GHz for a total of112 Gbps.

GPIO interfaces 210 include interfaces for a reference clock (RefClk), aset of joint test access group (JTAG) interfaces for a test clock (TCK),test reset (TRST), test mode select (TMS), test data in (TDI), test dataout (TDO), the set of JTAG interfaces collectively referred to as a testaccess port (TAP). Additional interfaces are described in Table 1listing the IO pad interfaces.

TABLE 1 Pin Name I/O Type Description Additional Information ETH_TXP0 .. . 67 OUT Pad SerDes Differential Single IO PAD per SerDes. Transmit(Positive) PAM4 encoding has 4 voltage level and will be represented inverilog as 2 bits. ETH_TXN0 . . . 67 OUT Pad SerDes Differential PAM4encoding has 4 Transmit voltage level and will be (Negative) representedin verilog as 2 bits. ETH_RXP0 . . . 67 IN Pad SerDes Differential PAM4encoding has 4 Transmit (Positive) voltage level and will be representedin verilog as 2 bits. ETH_RXN0 . . . 67 IN Pad SerDes Differential PAM4encoding has 4 Receive (Negative) voltage level and will be representedin verilog as 2 bits. ETH_REFCLKP IN Pad Ethernet Reference MainReference clock of clock (Differential SerDes Positive) ETH_REFCLKN INPad Ethernet Reference Main Reference clock of clock (DifferentialSerDes Negative) ETH_RESET_N IN Pad Asynchronous Asserted duringpower-on. Reset Driven from Main-die at interposer (1.8 V GPIO)REFCLK_OUT OUT Pad Reference clock Used to monitor output ETH_REFCLKP/Nthrough the clock observation pad located in main die. Driven fromMain-die at interposer (1.8 V GPIO) JTAG_TCK IN Pad JTAG Clock Drivenfrom Main-die at interposer (1.8 V GPIO) JTAG_TRST IN Pad JTAG ResetDriven from Main-die at interposer (1.8 V GPIO) JTAG_TMS IN Pad JTAG TMSDriven from Main-die at interposer (1.8 V GPIO) JTAG_TDI IN Pad JTAG TDIDriven from Main-die at interposer (1.8 V GPIO) JTAG_TDO_DAT OUT PadJTAG TDO DATA Driven from Main-die at interposer (1.8 V GPIO)JTAG_TDO_EN OUT Pad JTAG TDO Enable Driven from Main-die at interposer(1.8 V GPIO) JTAG_TDO OUT Pad JTAG TDO Driven from Main-die at (Tristateable) interposer (1.8 V GPIO) RPR_SI IN Pad Repair config chain Drivenfrom Main-die at in interposer (1.8 V GPIO) RPR_SO OUT Pad Repair configchain Driven from Main-die at out interposer (1.8 V GPIO) RPR_CLK IN PadRepair Clock Driven from Main-die at interposer (1.8 V GPIO) RPR_RST INPad Async reset only Driven from Main-die at for repair chain interposer(1.8 V GPIO) TEST_SI OUT Pad SCAN test Input Driven from Main-die atinterposer (1.8 V GPIO) TEST_SO0 OUT Pad SCAN test Output Driven fromMain-die at interposer (1.8 V GPIO) TEST_SO1 OUT Pad SCAN test OutputDriven from Main-die at interposer (1.8 V GPIO) TEST_SO2 OUT Pad SCANtest Output Driven from Main-die at interposer (1.8 V GPIO) TEST_SO3 INPad SCAN test Output Driven from Main-die at interposer (1.8 V GPIO)TEST_SE IN Pad SCAN test Enable Driven from Main-die at interposer (1.8V GPIO) TEST_SHIFT_CLK IN Pad SCAN test Driven from Main-die atinterface interposer (1.8 V GPIO) TEST_MODE IN Pad SCAN test Driven fromMain-die at interface interposer (1.8 V GPIO) TEST_RSVD0 IN Pad SCANtest Driven from Main-die at interface interposer (1.8 V GPIO)TEST_RSVD1 IN Pad SCAN test Driven from Main-die at interface interposer(1.8 V GPIO) TEST_EDT_UPDATE IN Pad SCAN test Driven from Main-die atinterface interposer (1.8 V GPIO) TEST_EXTEST_MODE IN Pad SCAN testDriven from Main-die at interface interposer (1.8 V GPIO) TEST_OCC_SI INPad SCAN test Driven from Main-die at interface interposer (1.8 V GPIO)TEST_OCC_SO OUT Pad SCAN test Driven from Main-die at interfaceinterposer (1.8 V GPIO)

Some IO pad interfaces in Table 1 are used for additional testing (e.g.,wafer-sort testing and testing at final assembled part level (e.g.,after mounting main and IO dies to silicon interposer)). The interfaces,in some embodiments, support (i) full TAP implementation (e.g.,supporting 1149.1, 1149.6, 1500, and 1687 protocols), (ii) eFuse macroand Fuse Controller, (iii) scan implementation, memory built-in selftest (BIST) and repair, (iv) loopback modes (e.g., testing from main dieinterface side and from the SerDes IO pad side), (v) robust interfacetesting (e.g., PRBS, BIST, etc.), (vi) data and clock redundancycontrol, (vii) boundary scan implementation, and (viii) characterizationsupport.

Auto-negotiation and link training modules 215 implementauto-negotiation primitives (e.g., low-level function of page receptionand transmission, better highest common denominator, forward errorcorrection resolution, etc.) for each SerDes. Modules 215, in someembodiments, also provide asymmetric auto-negotiation and link trainingsupport across a group of 400 Gbps SerDes (either eight 56 Gbps or four112 Gbps SerDes) with auto-negotiation and link training state machinefor transmit and receive slices having a mechanism to exchangeinformation. Link training is part of the SerDes die and is fullysupported by each SerDes lane. In some embodiments, automatic transitionfrom auto-negotiation to link training to mission mode are generatedthrough the management interface which reconfigures the SerDes to thenegotiated speed and trigger each function independently for each groupof SerDes (a group being associated to a MAC, for instance eight 56GSerDes for a 400G MAC).

The microbumps of the main die, in some embodiments, are arranged sothat they are mirrored on either side of the main die and rotationallyinvariant under a 180 degree rotation. IO dies, in some embodiments, aremounted in a first orientation to connect to a first side of the maindie and a second rotated (by 180 degrees) orientation to connect to asecond opposite side of the main die. In some embodiments, some SerDeslanes of the rotated die (e.g., a top- or bottom-most set of four 56Gbps SerDes) do not connect to the main die in one orientation.

A novel protocol for performing register read and write access fordifferent groups of SerDes (e.g., a group of 8 56 Gbps SerDes) within aSerDes die is provided for some embodiments. In some embodiments, thenovel protocol uses a set of 5 pins as a management interface includinga management clock input (MCI) sent from the main (core) die (tile) tothe IO die (tile), a management data input (MDI) of the IO die used tocommand, address, and write data, a management clock output (MCO) of theIO die that sends the MCI clock back from the IO die to the main die inorder to capture the management data output (MDO) from the main die, anda management data output (MDO) of the IO die used to read data back tothe main die. The protocol includes transactions for read transactions,write transactions, reset transactions, control and status register(CSR) access, and an interrupt transaction.

FIG. 3 depicts a set of connections 300 used by a single lane of aSerDes die (e.g., one 56 Gbps SerDes). FIG. 3 depicts the connectionslabeled by their functionality. The individual boxes 315 are organizedby their functionality, such as transmit (TX) connection group 305 andreceive (RX) connection group 310. Each numbered connection 315 may bethought of as a bit that makes up the 32 bit SerDes (with two extra bitsin each group of 32 bits for redundancy as is described below).Additional connections are made for a first transmit clock signal(TxClk), a second transmit clock signal (TxClkO) that is sent from theSerDes die to the main die for the main die to use as a transmit clocksignal, a receive clock signal (RxClk), as well as a set of VSSconnections, and a set of VDD connections. In the depicted embodiment,each clock signal has two connections, one primary connection and asecondary connection to provide redundancy because of the criticalnature of the clock signals, while data bits have one redundant bit forevery 16 bits. Thus, for the 32 bit data depicted in FIG. 3, twoadditional bits (e.g., bit 16 and bit 33) are provided as redundant bitsin the case of bit failure. Redundancy, in some embodiments, will beimplemented by muxing different data bits to adjacent micro bumps.Connections 315 marked PP are probe pad connections.

As shown, the connections in FIG. 3 are to be made with microbumpsorganized on the die edge. Data bits and clocks, in some embodiments,are organized in 5 rows of 8 columns of data with clocks in the middle.FIG. 3 depicts an inter-column distance of 37.5 microns and an inter-rowdistance of 40.32 microns. In some embodiments, the microbump pitch isapproximately 40 microns and the microbumps are arranged in equilateraltriangle configuration, such that column to column distance is 34.64microns. Microbumps are arranged in 20 columns and 40 rows for eachgroup of eight 56 Gbps SerDes in some embodiments.

In some embodiments, IO cells (CMOS buffers or inverters) are cell sizeD36 with ESD protection (50V CDM, 250V HBM), and 0.7V signaling. Wiringon the interposer, in some embodiments, uses redistribution layer (RDL)design rules with single-width, double-spacing (1W2S), with no need forshielding each wire in some embodiments. One of ordinary skill in theart would understand that instead of using 1W2S other embodiments usedouble-width, double-spacing (2W2S) or double-width, triple-spacing(2W3S). Special measures may need to be taken for clock signal routingsuch as 2W3 S and/or shielding.

FIG. 4 further depicts a set of 8 SerDes lanes (i.e., the eight 56 GbpsSerDes) that include the 5 connections for related management interfacesfor the group of 8 SerDes lanes. As depicted in FIG. 3, each lane has aset of connections for 32 bits of data in both a receive group andtransmit group (with an additional 2 bits of redundancy in each group)and clock connections. The central four lanes have additionalconnections for the management interfaces (including redundantconnections, as the management interfaces are critical connections).Thus, the set of eight SerDes requires a total of 602 microbumps to formthe connections with the described interfaces including 8 sets of (1) 34transmit bits (32+2 redundant), (2) 34 receive bits (32+2 redundant),(3) 2 bits for a transmit clock signal (TxClk), (4) 2 bits for atransmit clock signal (TxClkO), and (5) 2 bits for a receive clocksignal (RxClk), and a set of 10 management interface bits/microbumps (5primary and 5 redundant). In some embodiments, power and ground use anadditional 192 microbumps giving approximately 30% power to signal ratioand bringing the total number of microbumps used to 794 out of 800.

In some embodiments, the pin layout for a group of eight 56 Gbps SerDesis repeated eight times for the multiple sets of SerDes that make up theSerDes die. An additional group of four 56 Gbps SerDes is appended atone end of the SerDes die, and, in some embodiments, is not used for two(of four) of the SerDes dies attached to a main die. Thepins/connections for the group of 4 SerDes are symmetrical around acentral axis between two groups of two 56 Gbps SerDes and includepins/connections for a main management interface as well as a managementinterface for the four 56 Gbps SerDes.

FIG. 5 depicts one embodiment of a forwarding chip 500 that includessilicon interposer 515, SerDes tiles (dies) 520, and main (core) die525. Upper left SerDes tile 520 has 68-lanes numbered from 0 to 67,where lanes 0-3 are bottom most quad and lanes 64-67 are top most quad.The micro bump interface for these are presented such that bottom of theSerDes Tile has lane 0 and then other lanes in incremental order wheremicro bump interface for lane 67 is at the top edge. As shown in FIG. 5,lanes 64-67 are the four 56 Gbps SerDes group and are not attached forthe upper left and lower right SerDes tiles 520. By arranging the SerDestiles in this manner, the main (core) die 525 can have a symmetry aboutan axis running down the center of the die with the rotated SerDes diemaintaining the proper connections based on the symmetry of the eightand four 56 Gbps SerDes groups.

In some embodiments, SerDes tiles 520 and main die 525 are placed in aface-to-face arrangement with the silicon interposer to formmetal-to-metal connections between interfaces of the SerDes tiles 520and main die 525, and of the silicon interposer 515. In some embodimentseach of the interfaces of the silicon interposer 515 is a microbump. Insome embodiments, one or more of the SerDes tiles 520 and main die 525are placed in a face-to-back arrangement with the silicon interposersuch that the connections to between the die (e.g., SerDes tile 520 ormain die 525) and the silicon interposer is made through substrate ofthe die. Connections through a substrate, in some embodiments, includeconnections made using through silicon vias (TSVs) that connect the“back” of the substrate with interfaces of the “front” of the die.

FIG. 6 conceptually illustrates a process 600 for assembling aforwarding chip as described above. Process 600 begins by providing (at610) a substrate for the forwarding chip. In some embodiments, thesubstrate is a silicon interposer and wiring on the interposer usesredistribution layer (RDL) design rules with single-width,double-spacing (1W2S), with no need for shielding each wire in someembodiments. Special measures may need to be taken for clock signalrouting such as double-width, triple-spacing (2W3S) and/or shielding. Insome embodiments, the interposer uses three redistribution layers (RDL)for routing signals: top and bottom layers for signals, and the middlelayer as shield. In some embodiments, 65 nm process designs rules willbe used for the interposer, RDL metal using a width/spacing (W/S) equalto 0.4/0.4 microns and RDL VIA W/S equal to 0.36/0.34 microns, whilesingle-width, double-spacing (1W2S) non-default routing (NDR) will beused for chip to chip wires.

A main die comprising a switching (forwarding) fabric is then mounted(at 620) on the substrate. In some embodiments connections between thesubstrate and the main die are made using microbumps. Some embodimentsuse an inter-column distance of 37.5 microns and an inter-row distanceof 40.32 microns. In some embodiments, the microbump pitch isapproximately 40 microns and the microbumps are arranged in equilateraltriangle configuration, such that column to column distance is 34.64microns. Microbumps are arranged in 20 columns and 40 rows for eachgroup of eight 56 Gbps SerDes in some embodiments.

An IO die is mounted (at 630) to the substrate. The IO die, in someembodiments is a SerDes die (or tile) that provides an IO interfacebetween the main die and external sources. The SerDes die in someembodiments is similar to those described above in relation to FIGS. 1and 2. In some embodiments, the IO die converts a series of data bitsreceived from external sources into a set of parallel data bits that istransmitted to the main die, and converts a set of parallel data bitsreceived from the main die into a series of data bits that istransmitted to an external destination.

After the dies are mounted to the substrate the forwarding chip ispackaged (at 640) to protect it from external conditions. In someembodiments, packaging the chip includes introducing an encapsulant andor a chip case to protect the dies and the connections between the diesand substrate from environmental factors such as moisture and foreignparticles. It will be understood by one of skill in the art that theforwarding chip described above is attached to other chips in someembodiments and that alternative ordering of the die mounting steps maybe used.

Further details of the structure and function of the SerDes tile, insome embodiments, is presented below. In some embodiments, the SerDestile uses a source synchronous clocking scheme with data launch on therising edge of the clock while capture occurs on the following risingedge of the clock. Each chip validates timing by regular Static TimingAnalysis (STA) flow used for timing signoff. Chip to chip timing isvalidated using interposer extraction and flat chip to chipnetlist/standard parasitic exchange format (SPEF) data. In someembodiments, portions of the core chip and SerDes tile chip are blackboxed to optimize run time as long as it is not directly related to chipto chip interfaces being checked. Data and clock, in some embodiments,are forwarded from the tile to the core using a regular 1 cycle pathscheme. Data launches on the clock rise edge and is captured on the nextclock rising edge. For timing closure, a simple flop to flop 1 cyclepath scheme is used in some embodiments with adequate margins on setupand hold times.

Tiles, in some embodiments, use level shifters for main die interfacesignals in both directions. It is assumed that the main die in generalwill be smaller technology nodes and hence will have different Vdd/Gnd.For example: tile voltage is 0.9V for 28 nm, core voltage is 0.75V for 7nm, and proper level shifters are placed on both sides of the interfaceto take care of voltage difference and enable proper timing modeling.

As described above each 56G SerDes lane in some embodiments is 32b widewith a corresponding clock for receiving (Rx) and transmitting (Tx).Alternative speeds per SerDes in some embodiments are achieved withdifferent combinations of data width and parallel clock frequency (e.g.,112 Gbps using 64 bits and 1.8 GHz, 28 Gbps using 32 bits and 900 MHz,10.3125 Gbps using 16 bits and 644 MHz, or 1.25 Gbps using 8 bits and156.25 MHz). In some embodiments using 1.25 Gbps, a SerDes is programmedat 10 Gbps with eight times downsampling logic implemented in the IOtile logic.

FIG. 7 depicts different arrangements of SerDes tiles in embodiments ofthe forwarding chip that make use of different connections between theSerDes tiles and the Main die. Arrangement 705 reflects the embodimentdiscussed above in which each lane (e.g., set of 5 rows of microbumps720 and 725) connects 56 Gbps SerDes 730 to the main die. Arrangement710 is an alternative arrangement in which a single 112 Gbps SerDes 745uses both rows of microbumps 735. Each 112 Gbps 745 has 64 bits toconnect and the existing connections are made with 32 bit SerDes inmind. Thus, the connections for the second 112 Gbps 745 b (i.e.,microbumps 742) receive 32 bits of data meant for 112 Gbps SerDes 745 aand forwards them (e.g., through the silicon interposer) to the secondset of connections 740 b for the second 32 bits for 112 Gbps SerDes 745a. Arrangement 715 is an alternative design for 64 bit data processingby each 112 Gbps SerDes. Microbumps 750 (and the main dieinterfaces/pins) connect to microbumps 755 which in turn connect to two112 Gbps SerDes 760 for a next generation forwarding chip.

FIG. 8 illustrates a receive interface timing/waveform diagram using asource centered receive clock forwarding scheme. Receive clock atinternal node (rxclk int) 805 is shown with a rising edge at the originalong the time axis, the output receive clock (rxclk) 810 is shown withan offset defined by the flop and delay chain, while receive data(rxdata) 815 represents the 32 bits of data captured on the rising clockedge. In some embodiments, the clock for the 32-bit data group is sentsource synchronously. Data is delayed sufficiently through aprogrammable delay chain to enforce that data capture is always on therising clock edge immediately following that of the data launch. Alldata bits are shifted, when necessary, through a programmable delay lineon the clock generating the data at the launch side in order to fixpotential hold issues. For the SerDes receive data output interface, theIO Tile, in some embodiments, must flop the SerDes received data usingthe recovered clock rising edge for the entire data bus (32 b wide)before sending the data out to the microbumps. In some embodiments, theskew between the 32b Receive data bits must be tightly controlled andthe flop must be part of the structured placement of a given microbump.The clock for these launch flops is a delayed (by programmable delaychain) version of the recovered clock.

FIG. 9 illustrates a maximum setup and maximum hold timing budget namedrxclk_setup 975 and rxclk_hold 970. The programmable delay line isintended to fix hold timing issues on silicon (a debug feature). Eachbit of the 32-bit clock group (i.e., bits 925-950) is defined withmaximum setup and maximum hold timing budget named rxclk_setup andrxclk_hold. The original recovered clock is sent non-inverted as-is tothe clock microbump (physically 2 microbumps for redundancy) withoutadditional delays. This arrangement allows the Core Tile to capture thereceived data using the next rxclk rising edge.

In some embodiments, a SerDes tile sends its transmit phase locked loop(PLL) parallel clock (txclkO) to the core tile. The core tile uses thetxclkO internally to send the data out to the IO tile along with theclock txclk. The clock txclk is an as-is version of the txclkO. Thetransmit data generation logic in the core tile behaves exactly the sameas in the SerDes receive data output interface. FIG. 10 illustrates atransmit interface timing/waveform diagram using a source centeredtransmit clock forwarding scheme. SerDes transmit PLL parallel clock(txclkO) 1005 is shown with a rising edge at the origin along the timeaxis, the output transmit clock (txclk) 1010 is shown with an offsetdelay 1065, while transmit data (txdata) 1015 represents the 32 bits ofdata generated based on the rising clock edge.

In interacting with the core tile, in some embodiments, for the SerDestransmit data at the microbump interface, a single SerDes lane has aparallel interface that is 32-bit wide. The txclk 1010 and txdata 1015are generated by the core tile which received the SerDes transmit PLLparallel clock (txclkO) 1005 from the IO tile. The txclkO rising edgeclock is used to generate the 32-bit Tx data.

FIG. 11 illustrates txclk setup 1175 that defines the setup time betweenthe worst txdata bit 1145 and txclk 1120 rising edge and txclk hold 1170that defines the hold time between the worst txdata bit 1125 and txclkrising edge. The IO Tile must capture the received 32-bit Tx data usingthe rising edge of the txclk input clock 1120 before sending the data tothe SerDes Tx data parallel interface. The IO Tile must consider txclkOand txclk as mesochronous (0 ppm but unknown phase relationship) andthus implement a phase matching first in first out (FIFO) in thetransmit data path (due to each die temperature/voltage difference, thephase between txclkO and txclk may vary). This Tx phase matching FIFOwill avoid setup/hold issues.

FIG. 12 depicts a complete datapath for a Tx interface in someembodiments. FIG. 12 depicts 56 Gbps SerDes 1205, Tx phase matching FIFO1210, a set of pseudorandom binary sequence (PRBS) 23 checkers 1215,PRBS23 generator 1220, txclk 1225, txclkO 1230, txdata bits 1235, txclkcts 1240, and txclk int 1245. In some embodiments, the 32-bit Tx databits 1235 include 2 redundant signals (1 per group of 16-bits) (notshown) whereas each clock has a fully redundant microbump (equaling 2microbumps for txclkO 1230 and 2 microbumps for txclk 1225). Tx clocktxclk 1225 is used as the capture clock of the Tx data from the Core dieas well as the write clock to a phase matching FIFO 1210 (8 deep), whichconsiders the 2 clocks (txclkO 1230 and txclk 1225) as fullyasynchronous (but 0 ppm).

In order to check the sanity of the 32-bit Tx data group, in someembodiments, the IO Tile implements a pseudorandom binary sequence(PRBS) 23 checker 1215 across 32-bit data. In some embodiments, the PRBScheckers 1215 detects the PRBS invariant (all zeros) and considers thatpattern as all errors. The PRBS checkers 1215, in some embodiments, alsoloads the received data into the PRBS state every clock cycle, or onlywhen enabled in other embodiments. A PRBS23 generator 1220 is alsoimplemented before connecting to the SerDes Tx data path. The PRBS23generator 1220 is able to inject error through the register writeoperation. Both PRBS checker 1215 and generator 1220 are able to beenabled together (checking the data received from microbumps and sendinggenerated data on the SerDes Tx interface).

Each group of SerDes lanes, in some embodiments, has its associatedmanagement interface composed of 5 pins, (1) a management clock input(MCI) sent from the Core Tile to the IO Tile, (2) a management datainput (MDI) (of the IO Tile) used to send command, address, and writedata, (3) a management clock output (MCO) (of the IO Tile) that sendsback to the main die to capture MDO data output, (4) a management dataoutput (MDO) (of the IO Tile) that is used to receive read data back tothe core tile, and (5) an Interrupt (INT) output of the IO Tile.

FIG. 13 illustrates a datapath for management interface clocking. FIG.13 depicts main die 105, SerDes tile 110, MCI (1330), MDI (1335), MCO(1340), and MDO (#345) pins (datapaths) and a set of flip flops (1315,1325, 1350, and 1325) and lockup latches (1320 and 1360) used to managethe timing of the different register interfaces. In some embodiments,the MCI clock is derived by dividing the Main die clock by 4, 8, 16, or32 to limit the maximum interface frequency to 512 MHz or below. The MDIsignal conveys the management data from the main die to the SerDes IOTile and is generated on the same internal management clock rising edgeas the MCI clock sent along with the data. After the output flop 1315and before the MDI output buffer, a lockup latch 1320 is inserted toprovide a 50% hold time margin and a 50% setup margin (the MCI clock issource centered compared to the data). In the case of a timing issue,the MCI clock frequency can be divided by up to 32 (e.g., approximately50 MHz) for silicon debug adjustments.

The MCO clock is the MCI (input) clock sent back by the IO Tile to theMain die 105 in order to capture the MDO output data by the main die105. The MDO data is generated by the SerDes IO Tile 110 to convey theread/write acknowledgement of the transaction as well as the read datafor the Read operation. Similar to MCI/MDI, a lockup latch 1360 is addedafter the output flop 1355 driving the MDO output signal 1345 of the IOTile. The lockup latch effectively delays the MDO data by ½ clock cycleand thus guarantees a 50% hold margin and a 50% setup margin.

When there is no transaction, MDI signal is driven low by the Core Tile.Similarly, the MDO output of the Tile is asserted low by default. TheMDO output will only be driven high by the IO tile during the read orwrite transaction.

In some embodiments, a register transaction is always initiated by theCore Tile and is 28-bits or 44-bits long and always starts with apreamble (2b) followed by a type (2b), address (24b), and, for a writetransaction, data (16b). The preamble is the 2 bit Binary value ‘10’ insome embodiments. Similar to MDIO (but far from identical), a registertransaction is detected by the IO tile by detecting the Preamble on theMDI. Details of various transactions in some embodiments are providedbelow.

FIGS. 14A and 14B illustrate a timing diagram of a read operation (FIG.14A) and a read operation with timing error (FIG. 14B). A readtransaction is composed as follows, a 2-bit Preamble (e.g., ‘10’) (attime 1440), a 2-bit Type (e.g., ‘10’ opcode for read) (at time 1445),and a 24-bit address (at time 1450). A read transaction is completed bythe IO Tile through the MDO pin and includes a 2-bit Preamble/Status(e.g., ‘10’ for success, ‘11’ for error) (at time 1455) and a 16-bitread data (at time 1460). All read commands are non-posted, and the CoreTile must wait for an ACK/ERR response completion before initiating thenext command.

FIGS. 15A and 15B illustrate a timing diagram of a write operation (FIG.15A) and a write operation with timing error (FIG. 15B). A writetransaction is composed as follows, a 2-bit Preamble (e.g., ‘10’) (attime 1540), a 2-bit Type (e.g., ‘01’ opcode for write) (at time 1545), a24-bit address (at time 1550), and a 16-bit write data (at time 1555). Awrite transaction is completed by the IO Tile through the MDO pin andincludes a 2-bit Preamble/Status (‘10’ for success 1530 a, ‘11’ forerror 1530 b) (at time 1560).

All write commands are non-posted and the Core Tile must wait for anACK/ERR response before initiating the next command. In someembodiments, write completion is used to backpressure a stream of writetransaction. Every read/write operation, in some embodiments, iscompleted by the IO Tile either through a success status (‘10’) orthrough an error status (‘11’) within the time defined by the MDCINTERFACE TIMEOUT (128) MCI clock of the start of the transaction (fromthe end or previous transaction). Failure to achieve such requirementsmay potentially assert an interrupt in the Core Tile. The IO Tile alsoreturns an ERROR status, in some embodiments, when there is somethingun-expected from the core, for example, for some reason, when the 1^(st)set of 4 bits received from core is neither 1001 (write) nor 1010(read). Otherwise, the core can get stuck if tile does not returnanything.

FIG. 16 illustrates a timing diagram for a reset operation. FIG. 16includes a depiction of the output for the MCI 1605, the MDI 1620, theMCO 1625, and the MDO 1635. FIG. 16 also indicates the reset requestbeginning at time 1645 (after 64 high bits from the MDI), a resetacknowledgment beginning at time 1650, and a reset end beginning at time1655. In some embodiments, a reset transaction is enabled. For debugpurposes, a reset transaction, in some embodiments, is detected by theIO Tile when the MDI is asserted as high for 64 MCI clock cycles. Whensuch a transaction is detected, the IO Tile register interface mustperform a soft reset of its internal state machine and assert the MDOhigh for as long as MDI is asserted high. The MDO output is generatedfrom the flop output of the MCO clock within the maximum time defined byMCO2MDO, in some embodiments. The maximum skew allowed between MDC toMDI input flop (the difference between the path of the MDC to MDI inputflop CK pin and the path from the MDI to MDI input flop D pin) isdefined by the MCI2MDI time. The maximum frequency of MDC clock isdefined by the MCI_CLOCK_PERIOD time.

Based on the IO Tile requirement, the MCI clock, in some embodiments, isturned off outside of any transaction. The Core Tile guarantees aminimum of 4 clock cycles before the start of any transaction and afterthe end of any transaction (as seen by the Core Tile register interfaceFSM) in order to handle any potential corner case condition. The IOTile, in some embodiments, does not expect to have that MCI as a freerunning clock. However, the Core Die can guarantee 4 clocks are activebefore starting any transaction or after ending any transaction.

Assuming, for some embodiments, a MDC clock of 325 MHz, the registerinterface is able to perform one 16-bit register read/write operationevery 200 ns approximately. That should allow a 64 kB SerDes firmware toload in 6.4 ms approximately. For SerDes firmware loading, the writeinstruction (with broadcast address) is intended to be used for the casewhere the register interface is used to control multiple SerDes lanes.In some embodiments, the register interface also includes the INT outputpin of the IO Tile which should be asserted low by default (no interruptpending). When asserted high (level), the Core Main die will transferthe interrupt request to the system bus through an interrupt.

The interrupt mechanism, in some embodiments, is specified by the IOTile register specification but it must be accessible through theregister interface with standard interrupt handling functions, (e.g.interrupt statuses which are RW1C (Read/Write 1 to Clear), interruptenable, etc.). In some embodiments, the Interrupt Service Routine (ISR)must be able to find which interrupts have been asserted without pollingevery SerDes lane interrupt status register. Thus, in some embodiments,each register interface must contain a first level interrupt statusregister which will specify the indirection to a second level interruptstatus (which may be per lane or per function).

Each SerDes is able to provide critical status interrupts to theinterrupt mechanism, including interrupts for Tx PLL loss of lock (TxLOL), CDR loss of lock (Rx LOL), Rx Loss of Signal (not Rx Signal OK),Rx Signal Detected, Rx Not Ready, Tx Not Ready, Auto-Negotiationinterrupt, Link Training interrupt, etc. When any interrupt is asserted,the INT pin is asserted by the IO Tile until all interrupts are clearedby the ISR. The INT microbump is shared across 8 SerDes lanes (exceptfor the upper last 4. SerDes lanes) and the corresponding first levelInterrupt Status register (first register read by the ISR). For SerDesinterrupt and auto-negotiation/link training interrupt, a second levelinterrupt status per lane should report which type of interrupt has beenasserted.

Due to the flexible mapping of logical lane to independent physical Rxand Tx part of the SerDes function, the address map decode is logicaland not physical in some embodiments. Interrupt register mapping is alsological, not physical. Due to the Ethernet MAC IP requirement to get theRxSignalOK (Signal Detect or invert of loss-of-signal) information perSerDes lane accurately, the core die implements the hardware statemachine which automatically polls the RxSignalOK status of all 8 lanesbelonging to the same 400G MAC/PCS. This register is common to all 8SerDes lane (1 bit per lane) and assigned logically. The FSM will enablethe RxSignalOK as a virtual wire between the IO Tile and the Core die byregularly polling this common register. Similarly, any other informationwhich may need to be useful to the PCS/MAC (SerDes Ready), in someembodiments, is polled automatically. Such polling would need to bespecified by the IO Tile vendor through their IO Tile specificationdocument.

In some embodiments, the main die may decide to react on INT microbumpsignal assertion to process the loss-of-signal as a traditionalinterrupt (this will require the SerDes IO Tile to be able to report aninterrupt when SignalDetect reports either “loss of signal” or “signaldetected”). As each interrupt can be masked individually, the switch maydecide to rely on one mechanism or the other.

The main register interface is similar to the other managementinterfaces. In some embodiments, this main register interface enablesaccess to only top-level registers which are not SerDes (or a group of4/8 SerDes) specific. The main register interface, in some embodiments,cannot access SerDes registers. This main register interface programsthe logical to physical mapping of all SerDes lane for all group of 8SerDes (or 4. SerDes for the upper quad) and programs the referenceclock output going to the main die for clock observation purpose,trigger BIST, etc.

Both the main register interface and each management interface canaccess the internal system bus of the IO Tile. The System Bus, as wellas all SerDes Register Bus or logic controlling side band signals, areoperated out of the ETH_REFCLK_P/N differential clock running at 156.25MHz. That will require implementation of a clock domain crossing betweeneach Management interface MDC clock and system bus clock (each registerinterface only has one transaction at any given time which should makethis CDC simple).

The main register interface only addresses top-level registers and thusthe MSB address bit is not intended to be used as broadcast command. Insome embodiments, a SerDes IO Tile vendor provides a registerdescription for all top-level registers. The register interface has a24-bit address field that is a word address (word is defined as 2Bquanta corresponding to the 16-bit data bus width). Each managementinterface can only access 8 SerDes address spaces, which forces addressbit [22:19] to always be set to 0. For the upper register interface,which only has 4 SerDes, bit [22:18] will be forced to 0.

The 8 most significant address bits (MSB) of the management interfaceare used as follows: bit [23] is a broadcast bit when set, bit [22:16]are the SerDes ID. For the management interface of some embodiments, theSerDes ID will range from 0 to 7. Only the Broadcast Write operation ispermitted for the register interface (any Broadcast Read operationresult is undefined). That leaves 16-bit local addressing for eachSerDes (this is assuming that there is no common logic to a group of 8SerDes lanes). In embodiments that have a common logic to a group of 8SerDes lanes, those common registers are assigned to the logical SerDes0 address space, additional options will be understood by one of skillin the art.

For each register interface shared by 8 (4) SerDes, the main die willonly be able to address directly 128 KB. That leaves 16 KB per SerDeslane (assuming 8 SerDes maximum controlled by a single registerinterface). The SerDes ID which is the 3 MSB of the PCIe 128 KB addressspace will be mapped to register interface protocol address bit [18:16]and the PCIe address bit [13:2] will be mapped to the register interfaceprotocol bit [11:0]. That will leave bit [15:12] set to 0 for direct mapregister access (4K 16-bit register per SerDes can be directly mapped).

All upper SerDes registers (from 4K to 64K where address bit [15:12] arenon-zero) will be indirectly mapped. A single access to any of thoseregisters will take many PCIe register transactions (and handshakes on abusy bit). Thus, system performance will be reduced for those registers.Directly mapped registers are used for all functions used during missionmode of the SerDes, including Auto Negotiation, Link Training,Interrupts, etc. An indirectly mapped register is used for a debug/testor microcontroller firmware.

While the invention has been described with reference to numerousspecific details, one of ordinary skill in the art will recognize thatthe invention can be embodied in other specific forms without departingfrom the spirit of the invention. For instance, FIG. 6 conceptuallyillustrates a process. The specific operations of this process may notbe performed in the exact order shown and described. The specificoperations may not be performed in one continuous series of operations,and different specific operations may be performed in differentembodiments. Furthermore, the process could be implemented using severalsub-processes, or as part of a larger macro process.

What is claimed is:
 1. A forwarding chip comprising: a core firstapplication-specific integrated circuit (ASIC) die comprising switchingfabric to perform forwarding operations of the forwarding chip; aninput-output (IO) second ASIC die in communication with the core firstASIC die to serve as an IO interface of the core first ASIC die; asubstrate on which the first and second ASIC dies are mounted andthrough which they communicatively couple; and a chip encapsulatingmember for encapsulating the first and second ASIC dies and substrate ina chip housing, wherein: the input-output second ASIC die includes anarrangement of microbumps with associated functionality, the arrangementof microbumps with associated functionality is symmetrical about acentral axis of the input-output second ASIC die that separates a firsttop set of lanes and a second bottom set of lanes, and a microbump isassociated with a first functionality and a second microbump isassociated with a second and different functionality than that of thefirst functionality.
 2. The forwarding chip of claim 1 wherein thesubstrate comprises a silicon interposer through which the core firstASIC die connects to the input-output second ASIC die.
 3. The forwardingchip of claim 2, wherein the silicon interposer further comprises a setof microbumps used to form connections between the core first ASIC dieand the input-output second ASIC die.
 4. The forwarding chip of claim 1,wherein the core first ASIC die is a switching ASIC die.
 5. Theforwarding chip of claim 1, wherein the input-output second ASIC die isa serializer/deserializer (SerDes) ASIC die.
 6. The forwarding chip ofclaim 1, wherein the input-output second ASIC die is one of a pluralityof input-output ASIC dies connected to the core first ASIC die throughthe substrate.
 7. The forwarding chip of claim 23, wherein a thirdinput-output ASIC die in a plurality of input-output ASIC dies connectsto the core first ASIC die in an orientation that is rotatedapproximately 180 degrees around an axis normal to a surface of thethird input-output ASIC die relative to the input-output second ASICdie, so that the third input-output ASIC die connects to correctmicrobumps that form a connection between the core first ASIC die andthe third input-output ASIC die.
 8. The forwarding chip of claim 1,wherein the core first ASIC die uses a semiconductor processing nodesize that is less than a node size used by the input-output second ASICdie.
 9. The forwarding chip of claim 1, wherein connections to the corefirst ASIC die comprise: a first set of connections comprisingconnections for (i) a set of transmit bits and (ii) a set of transmitclock data, wherein the connections for the set of transmit bits arearranged around the connections for the set of transmit clock data; anda second set of connections comprising connections for (i) a set ofreceive bits and (ii) a set of receive clock data, wherein theconnections for the set of receive bits are arranged around theconnections for the set of receive clock data.
 10. The forwarding chipof claim 9, wherein a critical connection has a redundant connection,and wherein groups of noncritical connections share a redundant bit. 11.The forwarding chip of claim 10, wherein connections for clock data arecritical connections and connections for transmit and receive bits arenoncritical connections.
 12. A method of making a forwarding chippackage comprising: providing a substrate to support components of theforwarding chip package; mounting a core first application-specificintegrated circuit (ASIC) die to the substrate, the core first ASIC diecomprising a switching fabric for performing forwarding operations of aforwarding chip; mounting an input-output second ASIC die to thesubstrate to connect the input-output second ASIC die to the core firstASIC die, the input-output second ASIC die in communication with thecore first ASIC die for serving as an IO interface of the core firstASIC die; and encapsulating the substrate and the first and second ASICdies with an encapsulating member comprising a chip housing, wherein:the input-output second ASIC die includes an arrangement of microbumpswith associated functionality, the arrangement of microbumps withassociated functionality is symmetrical about a central axis of theinput-output second ASIC die that separates a first top set of lanes anda second bottom set of lanes, and a microbump is associated with a firstfunctionality and a second microbump is associated with a second anddifferent functionality than that of the first functionality.
 13. Themethod of claim 12, wherein the substrate includes a silicon interposerthrough which the core first ASIC die connects to the input-outputsecond ASIC die.
 14. The method of claim 13, wherein the siliconinterposer further comprises a set of microbumps used to formconnections between the core first ASIC and the input-output secondASIC.
 15. The method of claim 12, wherein the core first ASIC dieincludes a switching ASIC die.
 16. The method of claim 15, wherein theinput-output second ASIC die includes a serializer/deserializer (SerDes)ASIC die.
 17. The method of claim 16 further comprising: mounting aninput-output third ASIC die to the substrate to connect the input-outputthird ASIC die to the core first ASIC die.
 18. The method of claim 17,wherein an arrangement of microbump functionality on the core first ASICdie is mirrored on each of two sides of the core first ASIC die.
 19. Themethod of claim 18, wherein the input-output third ASIC die in aplurality of input-output ASIC dies is mounted in an orientation that isrotated approximately 180 degrees around an axis normal to a surface ofthe input-output third ASIC die relative to the input-output second ASICdie, so that the input-output third ASIC die connects to correctmicrobumps that form a connection between the core first ASIC die andthe input-output third ASIC die.
 20. The method of claim 12, whereinconnections to the core first ASIC die comprise: a first set ofconnections comprising connections for (i) a set of transmit bits and(ii) a set of transmit clock data, wherein the connections for the setof transmit bits are arranged around the connections for the set oftransmit clock data; and a second set of connections comprisingconnections for (i) a set of receive bits and (ii) a set of receiveclock data, wherein the connections for the set of receive bits arearranged around the connections for the set of receive clock data.